1. Field of the Invention
The present invention relates to multi-port memories generally and, more specifically, to emulated two-port memories using conventional single-port memories.
2. Description of the Related Art
Multi-port memories are widely used to allow substantially simultaneous access of the memory via two or more ports. For example, in data communication applications, packets for transmission or being received may be stored in a buffer, such as a FIFO buffer, prior to transmission or processing. Other applications include data scramblers and video graphics processors. Multi-port memories are generally characterized by the ability to write data to the memory on one port while simultaneously reading data on another port. One embodiment of a multi-port memory is a two-port memory, configured to allow read access on one dedicated port and write access on the other port, known generally as a single port read, single port write (1R1W) memory. Because implementing a true two-port memory can consume a large amount of area on a chip, many two-port memories, particularly those having more than a few tens of thousands of memory locations, are emulations utilizing banks of conventional single-port memories, known generally as single port Read/Write (1RW) memories. An emulated two-port memory might suffer from undesired latency should a simultaneous access of the same 1RW memory bank by both ports occur, such that repeated access of the same 1RW memory bank might result in a significant reduction in the rate the memory can be accessed by either port. Generally, the latency penalty for simultaneous access is one or more access or clock cycles. However, the amount of latency is dependant on memory access patterns and is not a fixed amount. More problematic is a simultaneous read and write to the same 1RW memory bank where the data being read is also overwritten, adding a data coherency issue on top of the latency and memory access rate problems.
One solution to the above problems is to “double pump” or access the 1RW memory bank twice in one clock cycle, e.g., doing the write in the first half of the cycle, then doing the read. However, this technique effectively requires that the memories run at twice the clock rate, limiting the speed of the two-port memory.
Thus, it is desirable to provide a two-port design that allows for simultaneous read and write with a low or fixed latency.